Conventional circuits are commonly formed from non-planar “fin” field effect transistors (finFETs). Conventional finFETs generally include multiple vertical fins serving as conducting channel regions. Conventional finFETs are not a gate-all-around (GAA) structure, and therefore gate control is only on sides of the fins, which limits gate length scaling.
Future technologies have contemplated inserting dielectric separation regions into the conducting channel region to divide or separate the fin into a series of stacked nanowire-like channel regions. These dielectric separation regions improve scaling of gate length by improving control of the channel potential compared to a conventional finFET without the dielectric separation regions. Improved channel control of the channel potential results from the gate coupling to each nanowire-like channel region through the dielectric separation regions at the top and bottom of each nanowire-like channel region in addition to the gate coupling to each nanowire-like channel region through the gate dielectric layers along the sides of each nanowire-like channel region. Additionally, the dielectric separation regions between portions of the fin increase the effective current drive per normalized height of the vertical sidewall conducting surfaces of the fin.
However, these dielectric separation regions between portions of the fin reduce the total height (i.e., summed height of each nanowire-like channel region) of the vertical sidewall conducting surfaces of the fin compared to a conventional finFET without the dielectric separation regions having the same total non-normalized structural height. Reducing the total height of the sidewall conducting surfaces may reduce the total current drive in the fin. Accordingly, inserting dielectric separation regions into the fin to create a series of stacked nanowire-like channel regions may result in a tradeoff between improving the scaling of gate length and reducing the total current drive per total non-normalized structural height.